1. Field of the Invention
The present invention relates to semiconductor integrated circuit that controls an oscillation frequency, and, more particularly to an all digital phased locked loop (ADPLL).
2. Description of the Related Art
In an intelligent integrated circuit (IC) in recent years, functions are integrated on the IC. It is not rare that a plurality of phase locked loops (PLLs) are mounted on the IC to allow the entire IC to operate with a single external clock. For example, when a desired clock is integer times as high as the external clock, a plurality of frequencies can be extracted from one oscillator. However, when a desired clock is not integer times as high as the external clock, a plurality of PLLs are necessary in a chip. Therefore, an area of the chip increases. It is becoming a general practice to mix, in a chip, a loop filter included in a PLL. In particular, an analog PLL in the past requires a large loop filter to prevent unnecessary radiation such as spurious radiation when a reference frequency is low or when low-frequency resolution of an oscillation frequency is requested. This causes an increase in a chip area. Therefore, when a plurality of PLLs are mounted on a chip, a further increase in a chip area is caused. In this way, an increase in functions and a reduction in a chip area are in a tradeoff relation.
To solve such a problem, for example, in a related art represented by JP-A. 2009-177685 (KOKAI), an ADPLL is used in which a reduction in a chip area is realized by replacing most of functions of a PLL with digitally-controlled functions.
However, an arithmetic unit occupies a large area in the ADPLL. When a plurality of the ADPLLs are used, a chip area increases in proportion to required specifications. Therefore, it is difficult to meet a need for a further reduction in a chip area.